Digital System Test And Testable Design: Using ... ✦ Popular

Gate-level faults, fault collapsing, and structural modeling in Verilog.

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Digital System Test and Testable Design: Using ...

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered

Logic BIST basics, test pattern generation, and output response analysis. The book by Zainalabedin Navabi (2010) is a

The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology

It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms. Memory fault models

Memory fault models, MBIST (Memory BIST) methods, and functional procedures.